At the moment the main reprogrammable Non Volatile Memories are based on the stacked floating-gate cell structure, and the industry make use of two architectures (see figure below):
- NOR Flash memories, characterized by faster access, but larger cell size, which are used mainly for code storage;
- NAND Flash memories, characterized by longer access times, and higher programming voltages, but with a smaller cell size, used mainly for data storage.
The definition NOR or NAND comes from the organization of the cells in the array.
In NOR configuration all cells are connected in parallel to a source line and, orthogonally, to a bit line. The cell transistor acts both as storage element and select transistor. Programming is performed by hot electron injection at the drain, while erasing takes place by Fowler-Nordheim tunnelling towards the accumulated substrate. This configuration allows for larger reading currents and faster access, but requires more area (roughly 9-12F2, where F is the half-pitch of the lithography node).
In NAND configuration the cells are connected in series in groups of 8 or 16, with select transistors at the end. Both programming and erasing take place by Fowler-Nordheim tunnelling from, or towards, the channel or the substrate. Reading currents are smaller because of the presence of several transistors in series, and programming is slower, but the cell area is smaller (4-5F2), and close to the theoretical limit for a memory.
Evolution of Flash memories is following the Moore’s law, and is now considered to be one of the main technology drivers in the ITRS roadmap, replacing DRAM in this function. The evolution of cell size has achieved a reduction of a factor of 30 in 10 years.
Mass storage solid state memories are realized exclusively with NAND memories, due to the lower cost per bit and higher programming throughput. The latter point, together with the cost, is the actual limiting factor for NOR memories in the mass-storage application. The Multi-Level Concept, i.e. the possibility to store two bits in one cell, has been proposed by Intel in the NOR technology to reduce the cost differential, but it is not competitive enough with the faster programming throughput of NAND. Moreover, also NAND technology has already started offering devices with 2bit/cell. The use of Multi-Level storage has its main drawbacks in reduced speed and reduced signal-to-noise ratio and error immunity. The latter can be solved by design, with Error Correction Algorithms, but introducing further delays in the access time. The main drawback of NAND memories is the relatively slow access speed. The problem can be partially solved by adding a buffer memory to improve throughput, therefore it is gaining increase acceptance the use of multi-chip memory modules, including in the same package a NAND Flash and a DRAM or SRAM.
With the above listed limitations, it now generally accepted that NAND technology will dominate mass-storage, while NOR technology will still be preferred for direct code execution.
The most recent achievement of floating gate storage is a 8Gb Multi-Level NAND cell developed in 63nm technology, announced by Samsung , with a cell size of 0.0164μm2 that fits well the predictions of ITRS roadmap. Nevertheless, the floating gate concept is predicted to face technological limits beyond the 40nm node, even if the limits for NAND cells could be pushed a little further than for NOR ones.
The main physical limits that prevent further scaling of the cells are:
cell to cell interference, due to the parasitic capacitive coupling among neighbouring floating gates;
low coupling ratio with the control gate, which results also in a small stored charge .
On the other side, trap-related leakage currents in the dielectrics prevent any scaling of the cell dielectrics, which could relieve this issue. Even now large NAND memories critically depend on the adoption of sophisticated error-correction algorithms to guarantee the target reliability, against the generation of point defects during the programming cycles. Further reduction of cell size will increase the requirements for error correction beyond the feasibility limits.
The most promising approach to overcome these scaling limitations, while retaining the very high integration density of NAND Flash architecture seems to be the replacement of the conventional floating gate with a charge trapping layer. Silicon nano-crystal trapping layers have been investigated in the past by some of the partners, but they present a few drawbacks, like reduced threshold shift and the presence of percolation paths between source and drain, that become more severe with the scaling of the cell size. 0
The best alternative seems to be the use of a continuous trapping layer, like Silicon Nitride in the SONOS device architecture because it solves several of the scalability issues:
the charge is trapped in a thin dielectric layer, and therefore there is no problem of capacitive interference among neighbouring cells;
since the charge is stored in electrically insulated traps, the device is also immune to SILC (Stress Induced Leakage Current), the parasitic leakage current caused by single defects in the dielectric layer, while in conventional floating gate devices even a single defect can discharge the whole floating gate, which is a conductive storage medium.
a reduction of the sensitivity to SILC could also allow simplifying error-correction algorithms, even if some caution is necessary, since new failure mechanisms could appear.
the replacement of the floating gate with a trapping layer reduces the overall thickness of the gate stack, and allows for an easier integration of the cell in the CMOS process.
In this architecture the charge is trapped in a Silicon Nitride layer, inserted between two Silicon Oxide layers, which act as tunnel dielectric (lower level) and blocking layer to prevent charge injection from the control gate (upper level), as shown in the figure below.
Cross-section and schematic band diagram for a SONOS memory cell
The device is programmed by Fowler-Nordheim charge tunnelling between the trapping layer and the substrate.
This architecture is known since the 80’s, but, after some initial success, and in spite of its better compatibility with standard CMOS process flow and lower costs, the SONOS approach lost ground in favour of the floating gate one, because of several fundamental problems:
Cell programming is limited by the erase saturation, which takes places because of the parasitic electron injection from the control gate through the top oxide, balancing the hole injection from the substrate;
Thinning the tunnel oxide (< 2.5nm) improves the threshold window and the programming speed, but results in poor retention, even at room temperature, because of direct tunnelling through the tunnel oxide, and charge mobility in the nitride layer;
Increasing the tunnel thickness improves the retention, but requires larger programming voltages, reduces the speed and activates the tunnelling through the top oxide.
In 2003, it was reported that the use of a high-k oxide (like Al2O3) as top dielectric could improve the erase saturation problems , thus allowing a thicker tunnel oxide and avoiding the retention issue. According to the paper, the use of a high-k blocking oxide enhances the field drop in the bottom oxide as compared to the blocking oxide, and thus injection of electrons from the gate is strongly limited. A further improvement can come from the use of a high Work Function metal gate because of the higher barrier height seen by electrons for gate injection .
Several other alternative approaches have been proposed for high density Non Volatile Memories, mostly based on resistivity modulation of different kinds of materials, but they all require the presence of a select transistor in series to the memory element, and therefore cannot reach the high density of NAND Flash and should be considered rather as an alternative to NOR Flash.
Therefore the state of the art for high density mass-storage solid state memories can be summarized as follows:
Floating gate NAND Flash is the dominating technology and has reached the level of 8Gbit (multi-level) in 63nm technology.
Further scaling of the floating gate architecture beyond the 40 nm technology node is considered unlikely.
A modified SONOS approach with high-k dielectric and metal gate (TANOS) is considered the most viable alternative.
However the introduction of the proposed innovations is far from being straightforward since it involves the adoption of several new materials (high-k dielectrics and metal gate), which resulted in new, unforeseen problems. As a consequence, the introduction of these materials has been considerably delayed even for conventional logic, which has much less severe leakage control problems.
Among the problems that need to be solved, we have to point out:
Improvement of material properties of the stack toward a more efficient charge trapping capability;
Development of materials with a higher dielectric constant than Al2O3 , for the blocking dielectric;
Improvement of the charge trapping layer in terms of energy depth and density of traps 7;
Metal gate development, namely its interface properties with the blocking layer, to obtain a high work function 5.
Optimization of the relative band-gap positions of the different layers composing the gate stack for the memory properties optimization ,
In-depth understanding of the charge trapping and parasitic conduction mechanism in the new layers;
Characterization and mitigation of the defect generation mechanisms during programming cycles.
Asymmetric distribution of the charge during writing and erasing cycles, or in consequence of parasitic programming, which could lead to performance degradation.
Moreover, even if dielectrics with higher dielectric constant than Al2O3 are known (e.g. HfO2, k~20), along with processing strategies for layers showing low leakage and high breakdown (atomic layer deposition, addition of Si, N), no combination of materials and processing has yet been found for suitable dielectrics of even higher capacitance density (k>40), which could significantly contribute to reach the most ambitious targets in the project. Therefore a careful optimization of the charge trapping cell, both at the layer material level as well as at the layers combination level and integration into a very aggressive lithography mode are key challenges for the success of NAND Flash beyond 40nm.
Just to give an idea of the sheer size of the problem to be faced, we should consider that the difference between acceptable cell leakage currents in between DRAM and Flash cells is around 10-11 orders of magnitude, the same difference in scale that exists between an atom and a man.
Another key consideration is that the new memory approach can be really competitive only if:
Deposition and processing conditions of new materials are compatible with the defect density required by multi-gigabit memories;
Enough understanding is reached of the different influence of trapping layers and interfaces in charge trapping during the programming cycles to allow for multi-level (at least 2bit/cell) storage.
For these reasons the project will also investigate multi-bit cells and 3D structures for even more advanced scaling.