Gossamer
Structure de mise en forme 2 colonnes
  • Tuesday 12 December 2017

  • Following the first promising results, in 2009 it was decided to anticipate a full industrial demonstrator, making use of the most advanced single exposure litho technology available.


     A 1 Gbit NAND memory device was modified by Numonyx to become compatible with the new cell architecture and fully functional samples have been obtained.

    First evaluation on the large statistical samples made available by the memory device did show good distribution of written and erased states, even if no programming algorithms were used to compensate for the threshold distribution, and confirmed the absence of cell to cell interference, which is the most important limit to NAND cell scaling. The device was used also to test new technology approaches to the cell architecture, introducing the Band Engineered Tunnel architecture (BET for short). Based on the replacement of the tunnel oxide by an oxide-nitride sandwich, the new structure allows for better programming characteristics and better reliability. Dedicated testing equipment has been developed for fast and reliable assessment of development memories, and it has been demonstrated on the 1Gbit device.

     

     


    In the course of the project it became evident that the original target of developing a 32nm generation technology was ambitious enough. Due to the faster than foreseen progress of conventional Flash devices, with 24nm devices entering production, it was decided to focus the effort in proving the scalability of the technology to the 20nm generation. At the same time a new trend was emerging for high density memories: 3-D architectures, and the partners decided to investigate this approach for TANOS memories.

     

     

     


    20nm technology


    Active cell size was scaled down in the 20-25nm range by using special lithographic techniques to extend the limits of available immersion lithography. Active area definition, high aspect ratio trench etching and filling and edge rounding problems were solved. A Self-Aligned Architecture was selected for the cell after extensive experimentation and modeling and a correct gate profile was achieved.


    In the end functional cell blocks were obtained. The same mask set used for the large scale demonstrator was processed. Due to the limitations of the lithography it was not possible to have fully functional samples of the 1Gbit demonstrator, but mini-arrays of 4Mbit, with simplified control circuitry were realized and successfully tested.

     

     

     

     

     

     

     


    Exploiting the third dimension


    Stacking memory cells in several layers is getting increased attention as a way to overcome lithography limitations. SONOS architectures are the only viable choice for these approaches. Therefore the partners have decided to include in the next step the exploration of architectures suitable for the 22nm node, exploiting the capability of 3D integration. Two approaches have been investigated.
    Vertical channel (Toshiba approach) has been investigated from IMEC and Fraunhofer-CNT. Several combinations of layers and etching steps have been tested for achieving a good bottom contact and preserving layer integrity. Basic functionality has been achieved of test structures (left).

     

     

     

     

     

     

    Multilayer stacking (Samsung approach) has been tested by Numonyx/Micron both with single crystal channels on SOI and polycrystalline channel on thermally grown oxide, and full rounded channel (right). Functional cells have been realized and characterized for performances and reliability.


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