Gossamer
Structure de mise en forme 2 colonnes
  • Wednesday 26 April 2017
  • 2008

    Understanding improved TANOS retention by material analysis of the SixNy trapping layer

     

     

     

    Aude Rothschild, G. Van den bosch, L. Breuil, A. Cacciato, H. Dekkers, E. Sleeckx, T. Conard, B. Brijs, J. A. Kittl

     

     

     

    IMEC

     

     

     

    214th Meeting of Electrochemical Society

     

     

     

    12/10/2008

     

     

     

    Honolulu, HI, USA

     

     

     

    Nitride engineering for improved erase performance and retention of TANOS NAND Flash memory

     

     

     

    Geert Van den bosch, A. Furnémont, L. Breuil, M. B. Zahid, R. Degraeve, A. Cacciato, A. Rothschild, C. Olsen, U. Ganguly, J. Van houdt

     

     

     

    IMEC

     

     

     

    23rd IEEE Nonvolatile Semiconductor Memory Workshop (NVSMW)

     

     

     

    18/05/2008

     

     

     

    Opio, France

     

     

     

    Improvement of TANOS NAND Flash performance by the optimization of a sealing layer

     

     

     

    Laurent Breuil, A. Furnémont, A. Rothschild, G. Van den bosch, A. Cacciato, J. Van Houdt

     

     

     

    IMEC

     

     

     

    23rd IEEE Nonvolatile Semiconductor Memory Workshop (NVSMW)

     

     

     

    18/05/2008

     

     

     

    Opio, France

     

     

     

    Materials selection, analysis and optimization for charge trap Flash memory stack

     

     

     

    Geert Van den bosch

     

     

     

    IMEC

     

     

     

    IMST2008 - EU Memory Technology Projects & Tutorials

     

     

     

    26/11/2008

     

     

     

    Leuven, Belgium

     

     

     

    Tutorial on Flash Memories

     

     

     

    Jan Van Houdt

     

     

     

    IMEC

     

     

     

    IMST2008 - EU Memory Technology Projects & Tutorials

     

     

     

    26/11/2008

     

     

     

    Leuven, Belgium

     

     

     

    Integration of Charge Trap Cell for NAND application: reasons, basic contraints and fundamental architectural choices

    Paolo Tessariol

     

    NUMONYX

     

    IMST2008 - EU Memory Technology Projects & Tutorials

     

    26/11/2008

     

    Leuven, Belgium

     

    Challenges of TANOS NAND string process integration

     

    Volkhard Beyer

     

    CNT/Qimonda

     

    IMST2008 - EU Memory Technology Projects & Tutorials

     

    26/11/2008

     

    Leuven, Belgium

     

    2009

    Investigation of window instability in program/erase cycling of TANOS NAND Flash memory

     

     

     

    Geert Van den bosch, L. Breuil, A. Cacciato, A. Rothschild, M. Jurczak, J. Van Houdt

     

     

     

    IMEC

     

     

     

    International Memory Workshop

     

     

     

    10/05/2009

     

     

     

    Monterey, USA

     

     

     

     

    TaN metal gate damage during high-k (Al2O3) high-temperature etch

    J. Paul, V. Beyer, P. Michalowski, M.F. Beug, L. Bach, M. Ackermann, S. Wege, A. Tilke,
    N. Chan, T. Mikolajick, U. Bewersdorff-Sarlette, R. Knöfler, M. Czernohorsky, C. Ludwig

     

     

     

     

     

    QD/CNT

     

     

     

     

     

     

    Microelectronic Engineering

     

     

     

     

    2009

     

     

     

    O2 post deposition anneal of Al2O3 blocking dielectric
    for higher performance and reliability of TANOS
    Flash memory

     

     

     

    A. Rothschild, L. Breuil, G. Van den bosch, O. Richard, T. Conard, A. Franquet, A. Cacciato, I. Debusschere, M. Jurczak, J. Van Houdt, J. A. Kittl, U. Ganguly, L. Date, P. Boelen, R. Schreutelkamp

     

     

     

    IMEC

     

     

     

    ESSDERC – ESSCIRC

     

     

     

    15/09/2009

     

     

     

    Athens, Greece

     

     

     

    Experimental Evaluation of Trapping Efficiency in
    Silicon Nitride Based Charge Trapping Memories

     

     

     

    A. Suhane, A. Arreghini, G. Van den bosch, L. Breuil, A. Cacciato, A. Rothschild, M. Jurczak, J. Van Houdt and K. De Meyer

     

     

     

    IMEC

     

     

     

    ESSDERC – ESSCIRC

     

     

     

    15/09/2009

     

     

     

    Athens, Greece

     

     

     

    The Role of the Substrate on the Atomic Layer Deposition of Alumina on Silicon Nitride, and its Oxides

     

     

     

    Maria-Elena Grillo

     

     

     

    TYNDALL

     

     

     

    Workshop on Computer simulation of oxides:
    Dopants, defects and surfaces

     

     

     

    09/09/2009

     

     

     

    Dublin, Ireland

     

     

     

    Stress Influence on TANOS Cell Performance

     

     

     

    Thomas Melde

     

     

     

    Qimonda, CNT

     

     

     

    IEEE International Memory Workshop (IMW),

     

     

     

    10/05/2009

     

     

     

    Monterey, USA

     

     

     

    Improvement of 48 nm TANOS NAND Cell Performance by Introduction of a Removable Encapsulation Liner

     

     

     

    Florian Beug

     

     

     

    Qimonda, CNT

     

     

     

    ECS Spring Meeting

     

     

     

    24/05/2009

     

     

     

    San Francisco, USA

     

     

     

    FIRST PRINCIPLES STUDY OF THE ATOMIC LAYER DEPOSITION OF ALUMINA ON SILICON NITRIDE, SILICON OXYNITRIDE AND SILICON DIOXIDE

     

     

     

    Simon Eliott, Maria Elena Grillo

     

     

     

    Tyndall

     

     

     

    Atomic Layer Deposition conference

     

     

     

    15/06/2009

     

     

     

    Uppsala, Sweden

     

     

     

    Formation of an interface layer between Al1-xSixOy thin films and the substrate during the rapid thermal annealing

     

     

     

    Paweł Piotr Michałowski, Volkhard Beyer, Malte Czernohorsky, Peter Kücher, Steffen Teichert, Gert Jaschke, Wolfhard Möller

     

     

     

    CNT

     

     

     

    ICFSI conference 2009

     

     

     

    05/07/2009

     

     

     

    Weimar, Germany

     

     

     

    Analysis of Trap Mechanisms responsible for
    Random Telegraph Noise and Erratic Programming
    on sub-50nm Floating Gate Flash Memories

     

     

     

    K. Seidel, R. Hoffmann, D. A. Löhr, T. Melde, M. Czernohorsky,
    J. Paul, M. F. Beug, and V. Beyer

     

     

     

    CNT, Namlab

     

     

     

    10th Annual Non-Volatile Memory Technology Symposium (NVMTS 2009)

     

     

     

    25/10/2009

     

     

     

    Portland, OR USA

     

     

     

    Electrical Analysis of Unbalanced Flash Memory
    Array Construction Effects and their impact on
    Performance and Reliability

     

     

     

     K. Seidel, T. Muller, T. Brandt, R. Hoffmann, D.A. Lohr, T. Melde, M. Czernohorsky, J. Paul, V. Beyer

     

     

     

    CNT, Namlab

     

     

     

    10th Annual Non-Volatile Memory Technology Symposium (NVMTS 2009)

     

     

     

    25/10/2009

     

     

     

    Portland, OR USA

     

     

     

    Improvement of 48 nm TANOS NAND Cell Performance by Introduction
    of a Removable Encapsulation Liner

     

     

     

    M. F. Beug, T. Melde, J. Paul, U. Bewersdorff-Sarlette, M. Czernohorsky, V. Beyer, R. Hoffmann,
    K. Seidel, D. A. Löhr, L. Bach, R. Knoefler, A. T. Tilke

     

     

     

    QD/CNT

     

     

     

    International Memory Workshop

     

     

     

    10/05/2009

     

     

     

    Monterey, CA , USA

     

     

     

    Characterisation of retention properties of charge-trapping memory cells at low temperatures

     

     

     

    E Yurchuk, J Bollmann and T Mikolajick

     

     

     

    TUBAF

     

     

     

    IOP Conference Series: Materials Science and Engineering

     

     

     

     

     

     

     

    Nancy, France

     

     

     

    Characterization of the diffusion process in Al2O3 thin films based on ToF-SIMS
    measurements

     

     

     

    P. P. Michalowski, M. Czernohorsky, V.d Beyer, G. Jaschke and S. Teichert

     

     

     

    CNT, Namlab

     

     

     

    DPG Frühjahrstagung 2009

     

     

     

    mars-09

     

     

     

    Dresden (Germany)

     

     

     

    Investigation of TaN and TiN metal gates during high-k (Al2O3) dry etch at elevated
    Temperatures

     

     

     

    J. Paul, V. Beyer, K. Biedermann, M. Mildner, E. Schuetze, T. Melde, M. Czernohorsky,
    S. Wege, M.F. Beug, R. Knoefler, T. Mikolajick

     

     

     

    CNT, Namlab

     

     

     

    35th International Conference on Micro-and Nano-Engineering,

     

     

     

    28/09/2009

     

     

     

    Ghent (Belgium)

     

     

     

    Simulation of hole and electron tunnel currents in MIS devices adopting the symmetric Franz-type dispersion relation for the charged carriers in thin insulators

     

     

     

    M. I. Vexler, A. Kuligk, B. Meinerzhagen

     

     

     

    TUBS

     

     

     

    Solid-State Electronics

     

     

     

    2009

     

     

     

     

     

     

     

    New materials in memory development sub 50nm: Trends in
    Flash and DRAM

     

     

     

    K. H. Kuesters, M. F. Beug, U. Schroeder, N. Nagel, U. Bewersdorff, G. Dallmann,
    S. Jakschik, R. Knoefler, S. Kudelka, C. Ludwig, D. Manger, W. Mueller, A. Tilke

     

     

     

    QD

     

     

     

    Advance Engineering materials

     

     

     

    2009

     

     

     

    Wiley-VCH Verlag GmbH & Co. KGaA

     

     

     

    Experimental and Simulation Analysis of
    Program/Retention Transients in Silicon
    Nitride Based NVM Cells

     

     

     

    Elisa Vianello, Francesco Driussi, Antonio Arreghini, Pierpaolo Palestri, David Esseni,

     

     

     

    IUNET

     

     

     

    Transaction on
    Electron Devices

     

     

     

    2009

     

     

     

     

     

     

     

    Select Device Disturb Phenomena in TANOS NAND Flash Memories

     

     

     

    Thomas Melde, Marc Florian Beug, Lars Bach, Armin Thomas Tilke,
    Roman Knoefler, Ulrike Bewersdorff-Sarlette, Volkhard Beyer, Malte Czernohorsky,
    Jan Paul, Thomas Mikolajick

     

     

     

    QD/CNT, TUBAF

     

     

     

    IEEE Electron Device Letters

     

     

     

    2009

     

     

     

     

     

     

     

    Franz Dispersion Relation for Tunneling Simulations in  polycrystaline-Silicon/SiO_2/Si_3N_4/SiO_2/Si and TaN/Al_2O_3/Si_3N_4/SiO_2/Si structures

     

     

     

    M.I. Vexler, A. Kuligk, B. Meinerzhagen

     

     

     

    TUBS

     

     

     

    Japanese Journal of Applied Physics

     

     

     

    2009

     

     

     

     

     

     

     

    Physical modeling for programming of TANOS memories in the Fowler-Nordheim regime

     

     

     

    Christian Monzio Compagnoni, Aurelio Mauri, Salvatore Amoroso,
    Alessandro Maconi, and Alessandro S. Spinelli

     

     

     

    Numonyx/IUNET

     

     

     

    Transaction Electron Device

     

     

     

    2009

     

     

     

     

     

     

     

    Experimental and Simulation Analysis of Program/Retention Transients in Silicon Nitride-Based NVM Cells

    E. Vianello, F. Driussi, A. Arreghini, P. Palestri, D. Esseni, L. Selmi, A. Akil, M. J. van Duuren, and D. S. Golubovic

    IUNET

    IEEE Transactions on Electron Devices (IEEE T. Electron. Dev.)

    2009

    Franz Dispersion Relation for Tunneling Simulations in  Polycrystaline-Silicon/SiO2/Si3N4/SiO2/Si and TaN/Al2O3/Si3N4/SiO2/Si Structures

    M.I. Vexler, A. Kuligk, and B. Meinerzhagen

    TUBS

    Japanese Journal of Applied Physics (Jpn. J. Appl. Phys.)

    2009

    TaN Metal Gate Damage During High-k (Al2O3) High-Temperature Etch

    J. Paul, V. Beyer, P. Michalowski, M.F. Beug, L. Bach, M. Ackermann, S. Wege, A. Tilke, N. Chan, T. Mikolajick, U. Bewersdorff-Sarlette, R. Knöfler, M. Czernohorsky, and C. Ludwig

    QD/CNT

    Microelectronic Engineering (Microelectron. Eng.)

    2009

    2010

    Improved high temperature etch processing of high-k metal gate stacks in scaled TANOS memory devices

     

     

     

    J. Paul, V. Beyer, M. Czernohorsky, M.F. Beug, K. Biedermann, M. Mildner, P. Michalowski, E. Schütze, T. Melde, S. Wege, R. Knöfler, T. Mikolajick

     

     

     

    CNT

     

     

     

    Microelectronic Engineering

     

     

     

    2010

     

     

     

     

     

     

     

    Validation of Retention Modeling as a Trap Profiling Technique for SiN based Charge Trapping Memories

     

     

     

    A. Suhane , A. Arreghini, R. Degraeve, G. Van den bosch, L. Breuil, M.B. Zahid, M. Jurczak,K. De Meyer  and J. Van Houdt

     

     

     

    IMEC

     

     

     

    IEEE Electron Device Letters

     

     

     

    2010

     

     

     

     

     

     

     

     

    A Consistent Explanation of the Role of the SiN Composition on the Program/Retention Characteristics of MANOS and NROM like Memories

     

     

    E.Vianello, E.Nowak, L.Perniola, F.Driussi, P.Blaise, G.Molas, B.De

     

    Salvo, and L.Selmi

     

     

     

     

    IUNET-Udine

     

    International Memory Workshop (IMW)

     

     

     

     

    May 2010

     

     

     

     

     

    Seoul, Korea

     

     

     

    Stack engineering of HfO2 –based charge trapping non volatile memory

    U. Russo, S. Spiga, G. Congedo, A. Lamperti, O. Salicio, M. Fanciulli

     

    MDM

     

    MRS Spring 2010 Meeting

     

    April 5-9, 2010

     

    San Francisco

     

    The Influence of Bottom Oxide Thickness on the Extraction of the Trap Energy Distribution in SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) Structures

    K. Bernert, C. Oestreich, J. Bollmann, and T. Mikolajick

    TUBAF

    Applied Physics A (Appl. Phys. A)

    2010

    Comprehensive Investigation of Statistical Effects in Nitride Memories – Part I: Physics-Based Modeling

    A. Mauri, C. M. Compagnoni, S. M. Amoroso, A. Maconi, A. Ghetti, A. S. Spinelli, and A. L. Lacaita

    NMX, IUNET

    IEEE Transactions on Electron Devices (IEEE T. Electron. Dev.)

    2010

    Comprehensive Investigation of Statistical Effects in Nitride Memories – Part II: Scaling Analysis and Impact on Device Performance

    C. M. Compagnoni, A. Mauri, S. M. Amoroso, A. Maconi, E. Greco, A. S. Spinelli, and A. L. Lacaita

    IUNET

    IEEE Transactions on Electron Devices (IEEE T. Electron. Dev.)

    2010

    Temperature Effects on Metal-Aluminanitride-Oxide-Silicon Memory Operations

    A. Padovani, L. Larcher, D. Heh, G. Bersuker, V. Della Marca, and P. Pavan

    IUNET

    Applied Physics Letter (Appl. Phys. Lett.)

    2010

    Analysis of TANOS Memory Cells with Sealing Oxide Containing Blocking Dielectric

    M. F. Beug, T. Melde, M. Czernohorsky, R. Hoffmann, J. Paul, R. Knöfler, and A. T. Tilke

    QD/CNT, Namlab

    IEEE Transactions on Electron Devices (IEEE T. Electron. Dev.)

    2010

    Explanation of the Charge Trapping Properties of Silicon Nitride Storage Layers for NVM’s – Part I: Experimental Evidences from Physical and Electrical Characterization

    E. Vianello, F. Driussi, L. Perniola, G. Molas, J.-P. Colonna, and L. Selmi

    IUNET Udine

    IEEE Transactions on Electron Devices (IEEE T. Electron. Dev.)

    2010

    Explanation of the Charge Trapping Properties of Silicon Nitride Storage Layers for NVM’s – Part II: Atomistic and Electrical Modeling

    E. Vianello, F. Driussi, P. Blaise, P. Palestri, D. Esseni,L. Perniola, G. Molas, and L. Selmi

    IUNET Udine

    IEEE Transactions on Electron Devices (IEEE T. Electron. Dev.)

    2010

    Experimental Assessment of Electrons and Holes in Erase Transient of TANOS and TANVaS Memories

    A. Suhane, A.  Arreghini, G.  Van den Bosch, L. Vandelli, A. Padovani, L. Breuil, L. Larcher, K. de Meyer, and J. van Houdt

    IMEC

    IEEE Electron Device Letters (IEEE Electron Dev. Lett.)

    2010

    2011

    Native Defects in Hexagonal β-Si3N4 Studied Using Density Functional Theory Calculations

    M.-E. Grillo, S. D. Elliott, and C. Freysoldt

    Tyndall

    Physical Review B (Phys. Rev. B)

    2011

    Charge Retention Phenomena in CT Silicon Nitride: Impact of Technology and Operating Conditions

    G. Ghidini, N. Galbiati, E. Mascellino, C. Scozzari, A. Sebastiani, S. Amoroso, C. Monzio Compagnoni, A.S. Spinelli, A. Maconi, R. Piagge, A. Del Vitto, M. Alessandri, I. Baldi, E. Moltrasio, G. Albini, A. Grossi, P. Tessariol, E. Camerlenghi, and A.Mauri

    NUMONYX/IUNET Milano

    Journal of Vacuum Science and Technology B (J. Vac. Sci. Technol. B)

    2011

    Synthesis and Characterization of DyScO Films Deposited on Si and Si-rich SiN by Atomic Layer Deposition for Blocking Layer Replacement in TANOS Stack

    A. Lamperti, E. Cianci, U. Russo, S. Spiga, O. Salicio, G. Congedo, and M. Fanciulli

    MDM, IMM-CNR

    Journal of Vacuum Science and Technology B (J. Vac. Sci. Technol. B)

    2011

    Evaluation of DyScOx as an Alternative Blocking Dielectric in TANOS Memories with Si3N4 or Si-rich SiN Charge Trapping Layers

    G. Congedo, S. Spiga, U. Russo, A. Lamperti, O. Salicio, E. Cianci, and M. Fanciulli

    MDM, IMM-CNR

    Journal of Vacuum Science and Technology B (J. Vac. Sci. Technol. B)

    2011

    Three-Dimensional Simulation of Charge-Trap Memory Programming – Part I: Average Behavior

    S. M. Amoroso, A. Maconi, A. Mauri, C. M. Compagnoni, A. S. Spinelli, and A. L. Lacaita

    IUNET-POLIMI and Micron

    IEEE Transactions on Electron Devices (IEEE T. Electron. Dev.)

    2011

    Three-Dimensional Simulation of Charge-Trap Memory Programming – Part II: Variability

    A. Maconi, S. M. Amoroso, C. M. Compagnoni, A. Mauri, A. S. Spinelli, and A. L. Lacaita

    IUNET-POLIMI and Micron

    IEEE Transactions on Electron Devices (IEEE T. Electron. Dev.)

    2011

    Stack Engineering of TANOS Charge-Trap Flash Memory Cell Using High-k ZrO2 Grown by ALD as Charge Trapping Layer

    G. Congedo, A. Lamperti, L. Lamagna, and S. Spiga

    MDM, IMM-CNR

    Microelectronic Engineering (Microelectron. Eng.)

    2011

    BE-TANOS: feasibility and technology limitations

    G.Ghidini, N.Galbiati, C.Scozzari, A.Sebastiani, R.Piagge, A.Del Vitto, P.Comite, M.Alessandri, P.Tessariol, I.Baldi, E.Moltrasio, E.Mascellino

    Numonyx

    Microelectronic Engineering (Microelectron. Eng.)

    2011

    Comprehensive Numerical Simulation of Threshold-Voltage Transients in Nitride Memoriesa

    A. Mauri, S. M. Amoroso, C. Monzio Compagnoni, A. Maconi, and A.S. Spinelli

    NMX

    Solid-State Electronics (Solid-State Electron.)

    2011