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  • Monday 08 March 2021
  • The project addresses for the first time the development of large size NAND Flash memories based on the charge trapping mechanism, instead of the conventional floating gate concept, for technology generations in the range of 36-28nm.

    The project was started in 2008 with the target to develop a NAND Flash memory technology for mass storage based on the charge trapping mechanism, instead of the conventional floating gate concept, addressing technology generations in the range of 36-28nm. The final objective of the project was to demonstrate the potential of the concept on demonstrator, realized by the industrial partners, with a target size close to the foreseen upper limit of the technology, in the order of the Gigabyte (=8 Gigabit).


    The target performances of the final demonstrators are illustrated in the table:

    Target Performances of final demonstrators




    Memory Size



    Target technology generation (litho dependent)



    Cell Area


    F2  (*)

    Programming Voltage



    Threshold Window



    Reading Current






    Retention time



    (*) F=technology node


    The motivation of the project was coming from the increasing demand for compact memory storage from a variety of ICT applications, mainly in the field of portable devices.

    One of the success factors of the solid-state Flash memories was not only their small cell size, but also their strong scalability that had enabled the continuous decrease of the cost per bit (Moore’s law), so that larger and larger memories have become affordable at very reasonable costs.

    Beside the economical importance of the market, which has been growing at a rate of more than 30% per year, the development of low cost solid-state mass-storage memories was seen as a critical enabling factor for other ICT segments, like:

    • Smart Phones

    • Digital Consumer Electronics

    • Portable computers

    • Portable information storage

    • Navigation Systems

    • Full medical records on one card

    • Data base for image recognition and biometric systems

    During the first year of the project it appeared evident that the evolution of the standard floating gate NAND technology was going to be faster than expected, with devices in the 30-35nm generation being announced by several companies. It was therefore decided to change the overall targets of the project, putting the final objective in the 22-25nm range (comparable with the expected state-of-the-art in 2011) and anticipating a first full size demonstrator of the technology in the available 45nm generation.


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