The work plan is strongly oriented towards the realization of two large scale demonstrators, which should prove the feasibility of the developed technology, and pave the way to the exploitation of the results of the project.
General specifications for the memory are defined by ITRS roadmap and by the projection of current technology trends. They will be updated inside the Management Work Package at the start of the projects, as part of the continuous benchmarking exercise, to take into consideration the possible evolution in technology from the date of preparation of the project.
The target specifications will drive the activity of the two Work Packages: WP1 - Material Development and WP2- Cell Architecture. The results will flow into the design and realization of two product-like demonstrators in WP4 - Demonstrator, together with the process flow and critical process steps developed in WP3 - Process Integration. Memory characterization and reliability will be two critical issues that will be covered in WP5 - Characterization and Reliability, including physical understanding and modelling of failure mechanisms, and development of appropriate characterization tools. WP6 - Higher Density Architectures will explore more risky approaches, which are likely to increase the performances of the technology, like new materials, 3-D cell structures and multi-bit storage. WP7 - Training and Dissemination will take care of the exploitation of the results of the project in terms of product development, IP generation and protection, scientific publications and upgrading of training courses.
The original plan was based on a duration of three year, with a final demonstrator in 32nm technology. During the course of the project it became evident that a more aggressive final target was required to match the evolution of the standard NAND Flash technology, and an extension to 42 months was requested to produce a final demonstration in the 22nm range.